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DATE
2006
IEEE
171views Hardware» more  DATE 2006»
16 years 25 days ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
16 years 25 days ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
16 years 25 days ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer
DFT
2006
IEEE
120views VLSI» more  DFT 2006»
16 years 25 days ago
On-Line Mapping of In-Field Defects in Image Sensor Arrays
Continued increase in complexity of digital image sensors means that defects are more likely to develop in the field, but little concrete information is available on in-field defe...
Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapma...
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
16 years 25 days ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...