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PCI
2005
Springer
15 years 11 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
PASTE
2010
ACM
15 years 11 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
JAR
2006
99views more  JAR 2006»
15 years 6 months ago
An Integrated Approach to High Integrity Software Verification
Using automated reasoning techniques, we tackle the niche activity of proving that a program is free from run-time exceptions. Such a property is particularly valuable in high inte...
Andrew Ireland, Bill J. Ellis, Andrew Cook, Roderi...
MINENET
2006
ACM
16 years 18 hour ago
SC2D: an alternative to trace anonymization
Progress in networking research depends crucially on applying novel analysis tools to real-world traces of network activity. This often conflicts with privacy and security requir...
Jeffrey C. Mogul, Martin F. Arlitt
CCS
2004
ACM
15 years 11 months ago
Web tap: detecting covert web traffic
As network security is a growing concern, system administrators lock down their networks by closing inbound ports and only allowing outbound communication over selected protocols ...
Kevin Borders, Atul Prakash