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» Improving the Performance of the RISE Algorithm
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JEA
2006
83views more  JEA 2006»
15 years 6 months ago
Cache-Friendly implementations of transitive closure
In this paper we show cache-friendly implementations of the Floyd-Warshall algorithm for the All-Pairs ShortestPath problem. We first compare the best commercial compiler optimiza...
Michael Penner, Viktor K. Prasanna
PARA
2004
Springer
16 years 3 days ago
Analyzing Advanced PDE Solvers Through Simulation
Abstract. By simulating a real computer it is possible to gain a detailed knowledge of the cache memory utilization of an application, e.g., a partial differential equation (PDE) s...
Henrik Johansson, Dan Wallin, Sverker Holmgren
156
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ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
16 years 3 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
DAC
2005
ACM
16 years 7 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
DAC
2010
ACM
15 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra