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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 7 days ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
161
Voted
ACMSE
2005
ACM
16 years 5 days ago
Facilitating and automating empirical evaluation
Through the automation of empirical evaluation we hope to alleviate evaluation problems encountered by software designers who are relatively new to the process. Barriers to good e...
Laurian Hobby, John Booker, D. Scott McCrickard, C...
LCPC
2004
Springer
15 years 12 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
LCN
2003
IEEE
15 years 12 months ago
Scheduling Resources in Programmable and Active Networks Based on Adaptive Estimations
In active and programmable networks, packet processing could be accomplished in the router within the data path. For efficient resource allocation in such networks, the packet sch...
Fariza Sabrina, Sanjay Jha
CODES
2004
IEEE
15 years 10 months ago
Dynamic overlay of scratchpad memory for energy minimization
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
Manish Verma, Lars Wehmeyer, Peter Marwedel