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HPCA
2009
IEEE
16 years 7 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
ICPP
2009
IEEE
16 years 1 months ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
SIGMOD
2009
ACM
269views Database» more  SIGMOD 2009»
16 years 6 months ago
Efficient approximate entity extraction with edit distance constraints
Named entity recognition aims at extracting named entities from unstructured text. A recent trend of named entity recognition is finding approximate matches in the text with respe...
Wei Wang 0011, Chuan Xiao, Xuemin Lin, Chengqi Zha...
MM
2006
ACM
181views Multimedia» more  MM 2006»
16 years 18 days ago
Towards content-based relevance ranking for video search
Most existing web video search engines index videos by file names, URLs, and surrounding texts. These types of video roughly describe the whole video in an abstract level without ...
Wei Lai, Xian-Sheng Hua, Wei-Ying Ma
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
16 years 7 days ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...