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MIDDLEWARE
2007
Springer
16 years 25 days ago
Using checkpointing to recover from poor multi-site parallel job scheduling decisions
Recent research in multi-site parallel job scheduling leverages user-provided estimates of job communication characteristics to effectively partition the job across multiple clus...
William M. Jones
TVLSI
2008
164views more  TVLSI 2008»
15 years 6 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
GLOBECOM
2010
IEEE
15 years 4 months ago
Performance Analysis of Dynamic Spectrum Access Networks under Primary User Emulation Attacks
Primary user emulation attack (PUEA) is a denial of service (DoS) attack unique to dynamic spectrum access (DSA) networks. While there have been studies in the literature to detect...
Z. Jin, S. Anand, K. P. Subbalakshmi
HPCA
2008
IEEE
16 years 7 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
PPAM
2007
Springer
16 years 24 days ago
Enhancing Productivity in High Performance Computing through Systematic Conditioning
Abstract. In order to take full advantage of high-end computing platforms, scientific applications often require modifications to source codes, and to their build systems that ge...
Magdalena Slawiñska, Jaroslaw Slawinski, Va...