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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 22 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
16 years 20 days ago
GISP: A Transparent Superpage Support Framework for Linux
Though all of the current main-stream OSs have supported superpage to some extent, most of them need runtime information provided by applications, simulator or other tools. Transp...
Ning Qu, Yansong Zheng, Wei Cao, Xu Cheng
LCTRTS
2007
Springer
16 years 13 days ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
16 years 10 days ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
EXPDB
2006
ACM
16 years 8 days ago
Pushing XPath Accelerator to its Limits
Two competing encoding concepts are known to scale well with growing amounts of XML data: XPath Accelerator encoding implemented by MonetDB for in-memory documents and X-Hive’s ...
Christian Grün, Alexander Holupirek, Marc Kra...
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