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IPPS
2006
IEEE
16 years 27 days ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
191
Voted
ISPASS
2006
IEEE
16 years 27 days ago
Comparing multinomial and k-means clustering for SimPoint
SimPoint is a technique used to pick what parts of the program’s execution to simulate in order to have a complete picture of execution. SimPoint uses data clustering algorithms...
Greg Hamerly, Erez Perelman, Brad Calder
ISPASS
2006
IEEE
16 years 27 days ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
171
Voted
IWPC
2006
IEEE
16 years 27 days ago
Dynamic Data Structure Analysis for Java Programs
Analysis of dynamic data structure usage is useful for both program understanding and for improving the accuracy of other program analyses. Static analysis techniques, however, su...
Sokhom Pheng, Clark Verbrugge
222
Voted
KBSE
2006
IEEE
16 years 27 days ago
A Portable Compiler-Integrated Approach to Permanent Checking
Program checking technology is now a mature technology, but is not yet used on a large scale. We identify one cause of this gap in the decoupling of checking tools from the everyd...
Eugen-Nicolae Volanschi
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