5273 search results - page 783 / 1055 » Improving quality together |
164
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
124
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
161
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
We propose a control theory-based dynamic voltage scaling (DVS) algorithm for interactive 3D game applications running on batterypowered portable devices. Using this scheme, we pe...
132
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
173
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DAC
1998
ACM
16 years 7 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...