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CF
2006
ACM
16 years 12 days ago
Kilo-instruction processors, runahead and prefetching
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...
Tanausú Ramírez, Alex Pajuelo, Olive...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 6 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
SIGMOD
2010
ACM
221views Database» more  SIGMOD 2010»
15 years 11 months ago
Low overhead concurrency control for partitioned main memory databases
Database partitioning is a technique for improving the performance of distributed OLTP databases, since “single partition” transactions that access data on one partition do no...
Evan P. C. Jones, Daniel J. Abadi, Samuel Madden
IEEEPACT
2006
IEEE
16 years 13 days ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
TVLSI
2008
150views more  TVLSI 2008»
15 years 5 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz