1001 search results - page 90 / 201 » Improving memory hierarchy performance for irregular applica... |
200
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ICS
2004
Tsinghua U.
15 years 11 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
187
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CASES
2006
ACM
16 years 12 days ago
2006
ACM
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
169
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USENIX
1993
15 years 7 months ago
1993
Robotic storage devices offer huge storage capacity at a low cost per byte, but with large access times. Integrating these devices into the storage hierarchy presents a challenge ...
160
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ICPP
2009
IEEE
16 years 1 months ago
2009
IEEE
— High-end computing (HEC) systems have passed the petaflop barrier and continue to move toward the next frontier of exascale computing. As companies and research institutes con...
126
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ISCA
1997
IEEE
15 years 10 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....