1001 search results - page 83 / 201 » Improving memory hierarchy performance for irregular applica... |
170
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HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
179
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
157
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TVCG
2010
15 years 1 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
227
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PPOPP
2011
ACM
14 years 9 months ago
2011
ACM
In recent years, GPUs have emerged as an extremely cost-effective means for achieving high performance. Many application developers, including those with no prior parallel program...
222
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SIGMETRICS
2008
ACM
15 years 6 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...