Sciweavers

1001 search results - page 77 / 201
» Improving memory hierarchy performance for irregular applica...
Sort
View
DEXA
2009
Springer
138views Database» more  DEXA 2009»
16 years 1 months ago
Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems
Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been ...
Yongkun Wang, Kazuo Goda, Masaru Kitsuregawa
SIGMETRICS
1996
ACM
174views Hardware» more  SIGMETRICS 1996»
15 years 10 months ago
Embra: Fast and Flexible Machine Simulation
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
Emmett Witchel, Mendel Rosenblum
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
16 years 1 months ago
A set-based mapping strategy for flash-memory reliability enhancement
—With wide applicability of flash memory in various application domains, reliability has become a very critical issue. This research is motivated by the needs to resolve the lif...
Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei...
ISCA
1993
IEEE
112views Hardware» more  ISCA 1993»
15 years 10 months ago
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors
The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with...
Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta
EUROPAR
2008
Springer
15 years 8 months ago
Low-Cost Adaptive Data Prefetching
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hie...
Luis M. Ramos, José Luis Briz, Pablo E. Ib&...