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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
16 years 1 days ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ESTIMEDIA
2004
Springer
15 years 11 months ago
Data assignment and access scheduling exploration for multi-layer memory architectures
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
15 years 11 months ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
SAMOS
2010
Springer
15 years 4 months ago
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...
Oliver Arnold, Gerhard Fettweis
WMPI
2004
ACM
15 years 12 months ago
Memory coherence activity prediction in commercial workloads
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...
Stephen Somogyi, Thomas F. Wenisch, Nikolaos Harda...