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CODES
2011
IEEE
14 years 6 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
PLDI
2012
ACM
13 years 8 months ago
Speculative separation for privatization and reductions
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
Nick P. Johnson, Hanjun Kim, Prakash Prabhu, Ayal ...
ECAI
2006
Springer
15 years 10 months ago
Environment-Driven Skeletal Plan Execution for the Medical Domain
An important application of both data abstraction and plan execution is the execution of clinical guidelines and protocols (CGP), both to validate them against a large set of test ...
Peter Votruba, Andreas Seyfang, Michael Paesold, S...
ASPLOS
2009
ACM
16 years 7 months ago
Understanding software approaches for GPGPU reliability
Even though graphics processors (GPUs) are becoming increasingly popular for general purpose computing, current (and likely near future) generations of GPUs do not provide hardwar...
Martin Dimitrov, Mike Mantor, Huiyang Zhou
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 11 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...