1001 search results - page 141 / 201 » Improving memory hierarchy performance for irregular applica... |
142
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DATE
2008
IEEE
16 years 23 days ago
2008
IEEE
This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using ...
149
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IEEEPACT
1998
IEEE
15 years 10 months ago
1998
IEEE
Method speculation of object-oriented programs attempts to exploit method-level parallelism (MLP) by executing sequential method invocations in parallel, while still maintaining c...
178
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EGH
2004
Springer
15 years 11 months ago
2004
Springer
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
156
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
168
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IPPS
2006
IEEE
16 years 10 days ago
2006
IEEE
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...