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IEEEPACT
2006
IEEE
16 years 10 days ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
VLDB
1999
ACM
145views Database» more  VLDB 1999»
15 years 10 months ago
DBMSs on a Modern Processor: Where Does Time Go?
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
15 years 10 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
16 years 23 days ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti
BTW
2005
Springer
112views Database» more  BTW 2005»
15 years 12 months ago
Valid Updates for Persistent XML Objects
: XML has emerged as the industry standard for representing and exchanging data and is already predominant in several applications today. Business, analytic and structered data wil...
Henrike Schuhart, Volker Linnemann