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DATE
2003
IEEE
92views Hardware» more  DATE 2003»
15 years 11 months ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
CODES
2005
IEEE
16 years 18 hour ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
POPL
2007
ACM
16 years 6 months ago
A concurrent constraint handling rules implementation in Haskell with software transactional memory
Constraint Handling Rules (CHR) is a concurrent committedchoice constraint logic programming language to describe transformations (rewritings) among multi-sets of constraints (ato...
Edmund S. L. Lam, Martin Sulzmann
IPPS
2009
IEEE
16 years 1 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
ISPASS
2009
IEEE
16 years 1 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...