Sciweavers

1001 search results - page 106 / 201
» Improving memory hierarchy performance for irregular applica...
Sort
View
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
15 years 1 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
PLDI
2005
ACM
15 years 12 months ago
Garbage collection without paging
Garbage collection offers numerous software engineering advantages, but interacts poorly with virtual memory managers. Existing garbage collectors require far more pages than the ...
Matthew Hertz, Yi Feng, Emery D. Berger
ISCA
2009
IEEE
158views Hardware» more  ISCA 2009»
16 years 1 months ago
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
Carlos Madriles, Pedro López, Josep M. Codi...
ASPLOS
2010
ACM
16 years 27 days ago
COMPASS: a programmable data prefetcher using idle GPU shaders
A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores...
Dong Hyuk Woo, Hsien-Hsin S. Lee
IPPS
2007
IEEE
16 years 21 days ago
Incorporating Latency in Heterogeneous Graph Partitioning
Parallel applications based on irregular meshes make use of mesh partitioners for efficient execution. Some mesh partitioners can map a mesh to a heterogeneous computational plat...
Eric E. Aubanel, Xiaochen Wu