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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
16 years 3 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
ICASSP
2009
IEEE
16 years 1 months ago
Improving multi-lattice alignment based spoken keyword spotting
In previous work, we showed that using a lattice instead of the 1-best path to represent both the query and the utterance being searched is beneficial for spoken keyword spotting...
Hui Lin, Alex Stupakov, Jeff Bilmes
ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
16 years 25 days ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
IJCNLP
2005
Springer
16 years 9 days ago
Improving Korean Speech Acts Analysis by Using Shrinkage and Discourse Stack
Abstract. A speech act is a linguistic action intended by a speaker. It is important to analyze the speech act for the dialogue understanding system because the speech act of an ut...
Kyungsun Kim, Youngjoong Ko, Jungyun Seo
GECCO
2004
Springer
16 years 6 days ago
Improving the Locality Properties of Binary Representations
Abstract. Choosing representations and operators that preserve locality between genotype and phenotype space is an important goal in EA design. In the GA literature there has been ...
Adrian Grajdeanu, Kenneth A. De Jong