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DATE
2010
IEEE
140views Hardware» more  DATE 2010»
15 years 11 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
George Economakos, Sotirios Xydis, Ioannis Koutras...
SIGGRAPH
1999
ACM
15 years 11 months ago
Optimization of Mesh Locality for Transparent Vertex Caching
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
Hugues Hoppe
152
Voted
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 11 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
180
Voted
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 10 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
CARDIS
2006
Springer
114views Hardware» more  CARDIS 2006»
15 years 10 months ago
A Low-Footprint Java-to-Native Compilation Scheme Using Formal Methods
Ahead-of-Time and Just-in-Time compilation are common ways to improve runtime performances of restrained systems like Java Card by turning critical Java methods into native code. H...
Alexandre Courbot, Mariela Pavlova, Gilles Grimaud...