Sciweavers

5523 search results - page 720 / 1105
» Improving application performance with hardware data structu...
Sort
View
DAC
2007
ACM
16 years 7 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
Pramod Chandraiah, Rainer Dömer
ALGORITHMICA
2010
127views more  ALGORITHMICA 2010»
15 years 6 months ago
An Algorithm for Minimum Cost Arc-Connectivity Orientations
Given a 2k-edge-connected undirected graph, we consider to find a minimum cost orientation that yields a k-arc-connected directed graph. This minimum cost k-arc-connected orientat...
Satoru Iwata, Yusuke Kobayashi
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
16 years 24 days ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
SI3D
2006
ACM
16 years 21 days ago
Interactive 3D distance field computation using linear factorization
We present an interactive algorithm to compute discretized 3D Euclidean distance fields. Given a set of piecewise linear geometric primitives, our algorithm computes the distance...
Avneesh Sud, Naga K. Govindaraju, Russell Gayle, D...
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
16 years 1 days ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar