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PDPTA
2000
15 years 8 months ago
Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
Mayez A. Al-Mouhamed, Husam Abu-Haimed
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
16 years 1 months ago
Adaptive prefetching for shared cache based chip multiprocessors
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk
FPL
2004
Springer
171views Hardware» more  FPL 2004»
16 years 4 days ago
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed...
David V. Schuehler, John W. Lockwood
KDD
2004
ACM
114views Data Mining» more  KDD 2004»
16 years 7 months ago
Mining reference tables for automatic text segmentation
Automatically segmenting unstructured text strings into structured records is necessary for importing the information contained in legacy sources and text collections into a data ...
Eugene Agichtein, Venkatesh Ganti
CAISE
2005
Springer
16 years 9 days ago
BInXS: A Process for Integration of XML Schemata
This paper presents a detailed integration process for XML schemata called BInXS. BInXS adopts a global-as-view integration approach that builds a global schema from a set of heter...
Ronaldo dos Santos Mello, Carlos A. Heuser