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IEEEPACT
2008
IEEE
16 years 1 months ago
Adaptive insertion policies for managing shared caches
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...
Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qu...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
16 years 1 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
DATE
2009
IEEE
124views Hardware» more  DATE 2009»
16 years 1 months ago
Design and implementation of scalable, transparent threads for multi-core media processor
—In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the num...
Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyosh...
ISPASS
2007
IEEE
16 years 1 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
JUCS
2006
95views more  JUCS 2006»
15 years 6 months ago
POCA : A User Distributions Algorithm in Enterprise Systems with Clustering
Abstract: As enterprises worldwide race to improve real-time management to improve productivity, customer services and flexibility, huge resources have been invested into enterpris...
Ping-Yu Hsu, Ping-Ho Ting