1045 search results - page 28 / 209 » Improving SHA-2 Hardware Implementations |
160
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ISM
2008
IEEE
16 years 10 days ago
2008
IEEE
Many multimedia applications rely on the computation of logarithms, for example, when estimating log-likelihoods for Gaussian Mixture Models. Knowing of the demand to compute loga...
177
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DAC
2005
ACM
16 years 6 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
172
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FCCM
2004
IEEE
15 years 9 months ago
2004
IEEE
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
185
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FCCM
2006
IEEE
15 years 12 months ago
2006
IEEE
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
149
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ICCD
1997
IEEE
15 years 10 months ago
1997
IEEE
In this paper, we present a parallel-array implementation of a new non-restoring square root algorithm (PASQRT). The carry-save adder (CSA) is used in the parallel array. The PASQ...