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IEEEPACT
2005
IEEE
16 years 12 days ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
177
Voted
IPPS
2005
IEEE
16 years 12 days ago
Power and Energy Profiling of Scientific Applications on Distributed Systems
Power consumption is a troublesome design constraint for emergent systems such as IBM’s BlueGene /L. If current trends continue, future petaflop systems will require 100 megawat...
Xizhou Feng, Rong Ge, Kirk W. Cameron
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
16 years 12 days ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
16 years 11 days ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ITCC
2005
IEEE
16 years 11 days ago
Zonal Rumor Routing for Wireless Sensor Networks
has to be relayed to nodes interested in those events. Moreover, nodes may also generate queries to find events they are interested in. Thus there is a need to route the informatio...
Tarun Banka, Gagan Tandon, Anura P. Jayasumana
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