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179
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
180
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
191
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ISVLSI
2007
IEEE
16 years 1 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
162
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MICRO
2007
IEEE
16 years 1 months ago
2007
IEEE
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
195
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SECON
2007
IEEE
16 years 1 months ago
2007
IEEE
—In this paper, we develop a joint Network Coding (NC)-channel coding error-resilient sensor-network approach that performs In-Network Processing based on channel code Design (IN...