328 search results - page 65 / 66 » Improving Performance of Small On-Chip Instruction Caches |
177
click to vote
ISCA
1994
IEEE
15 years 10 months ago
1994
IEEE
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
153
click to vote
SIGGRAPH
2009
ACM
16 years 15 days ago
2009
ACM
We present a novel bounding volume hierarchy (BVH) compression and decompression method transparently supporting random access on the compressed BVHs. To support random access on ...
172
click to vote
HPCA
2002
IEEE
16 years 6 months ago
2002
IEEE
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
148
click to vote
CLUSTER
2007
IEEE
15 years 10 months ago
2007
IEEE
Bulk memory copies incur large overheads such as CPU stalling (i.e., no overlap of computation with memory copy operation), small register-size data movement, cache pollution, etc...
174
click to vote
MICRO
2008
IEEE
16 years 11 days ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...