328 search results - page 60 / 66 » Improving Performance of Small On-Chip Instruction Caches |
159
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CASES
2007
ACM
15 years 10 months ago
2007
ACM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
167
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JILP
2000
15 years 5 months ago
2000
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
166
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ICCD
2004
IEEE
16 years 2 months ago
2004
IEEE
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
194
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ASPLOS
2010
ACM
15 years 9 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
156
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ASPLOS
2010
ACM
16 years 26 days ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...