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» Improving Java performance using hardware translation
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WMPI
2004
ACM
15 years 12 months ago
Evaluating kilo-instruction multiprocessors
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. ...
Marco Galluzzi, Ramón Beivide, Valentin Pue...
IEEEPACT
2009
IEEE
16 years 1 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
16 years 24 days ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 11 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
16 years 3 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...