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DAC
1989
ACM
15 years 10 months ago
Scheduling and Binding Algorithms for High-Level Synthesis
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
Pierre G. Paulin, John P. Knight
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
15 years 11 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DATE
2003
IEEE
85views Hardware» more  DATE 2003»
15 years 11 months ago
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
Symbolic techniques usually use characteristic functions for representing sets of states. Boolean functional vectors provide an alternate set representation which is suitable for ...
Amit Goel, Randal E. Bryant
DSD
2003
IEEE
107views Hardware» more  DSD 2003»
15 years 11 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf