2032 search results - page 212 / 407 » Improving Java performance using hardware translation |
150
click to vote
ICCAD
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
188
click to vote
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
152
click to vote
ISCA
2000
IEEE
15 years 11 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
167
click to vote
MICRO
2010
IEEE
15 years 4 months ago
2010
IEEE
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
170
click to vote
MICRO
2006
IEEE
16 years 16 days ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...