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ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
16 years 24 days ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
FPL
2007
Springer
78views Hardware» more  FPL 2007»
16 years 20 days ago
Dynamic Cache Switching in Reconfigurable Embedded Systems
The idea of changing cache attributes to suit an application has been explored for single programs. As the popularity of reconfigurable softcore systems grows and these systems in...
John Shield, Peter Sutton, Philip Machanick
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
16 years 17 days ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
15 years 11 months ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko
ISCAS
1999
IEEE
131views Hardware» more  ISCAS 1999»
15 years 10 months ago
A multilevel modulation scheme for high-speed wireless infrared communications
To investigate short-distance, point-to-point, infrared channels, a test-bench and circuits were constructed to determine the limitations ofexisting optoelectronics. Theresults of...
S. Hranilovic, D. A. Johns