Sciweavers

2032 search results - page 206 / 407
» Improving Java performance using hardware translation
Sort
View
ICCAD
2005
IEEE
199views Hardware» more  ICCAD 2005»
16 years 3 days ago
FinFETs for nanoscale CMOS digital integrated circuits
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
Tsu-Jae King
DATE
1998
IEEE
82views Hardware» more  DATE 1998»
15 years 10 months ago
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
ERSA
2006
89views Hardware» more  ERSA 2006»
15 years 8 months ago
Multi-Mode Operator for SHA-2 Hash Functions
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arn...
EUROPAR
1999
Springer
15 years 10 months ago
An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors
Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism ILP techniques that are traditionally used in high perform...
Daniel A. Connors, Jean-Michel Puiatti, David I. A...
ISCA
2007
IEEE
115views Hardware» more  ISCA 2007»
16 years 24 days ago
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...
Hyesoon Kim, José A. Joao, Onur Mutlu, Chan...