Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arn...
Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism ILP techniques that are traditionally used in high perform...
Daniel A. Connors, Jean-Michel Puiatti, David I. A...
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...