2032 search results - page 205 / 407 » Improving Java performance using hardware translation |
181
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ISCA
2008
IEEE
16 years 27 days ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
140
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
189
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation...
164
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ISCA
2008
IEEE
16 years 27 days ago
2008
IEEE
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
180
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DDECS
2009
IEEE
16 years 1 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...