2032 search results - page 201 / 407 » Improving Java performance using hardware translation |
169
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ISCA
2007
IEEE
16 years 24 days ago
2007
IEEE
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
195
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FASE
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Atomicity violation, which is ...
156
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FCCM
2007
IEEE
16 years 25 days ago
2007
IEEE
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
166
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
158
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IEEEPACT
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...