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» Improving Java performance using hardware translation
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ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
15 years 10 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
MICRO
1994
IEEE
123views Hardware» more  MICRO 1994»
15 years 10 months ago
The effects of predicated execution on branch prediction
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
Gary S. Tyson
ACSD
2004
IEEE
118views Hardware» more  ACSD 2004»
15 years 10 months ago
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Fur...
ATVA
2008
Springer
104views Hardware» more  ATVA 2008»
15 years 8 months ago
A Direct Algorithm for Multi-valued Bounded Model Checking
Multi-valued Model Checking is an extension of classical, two-valued model checking with multi-valued logic. Multi-valuedness has been proved useful in expressing additional inform...
Jefferson O. Andrade, Yukiyoshi Kameyama
IWMM
2010
Springer
125views Hardware» more  IWMM 2010»
15 years 8 months ago
Efficient memory shadowing for 64-bit architectures
Shadow memory is used by dynamic program analysis tools to store metadata for tracking properties of application memory. The efficiency of mapping between application memory and s...
Qin Zhao, Derek Bruening, Saman P. Amarasinghe