Sciweavers

2032 search results - page 196 / 407
» Improving Java performance using hardware translation
Sort
View
HPCA
2003
IEEE
16 years 6 months ago
Dynamic Data Dependence Tracking and its Application to Branch Prediction
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Lei Chen, Steve Dropsho, David H. Albonesi
ICCD
2004
IEEE
99views Hardware» more  ICCD 2004»
16 years 3 months ago
An Efficient Algorithm for Reconfiguring Shared Spare RRAM
Redundant rows and columns have been used for years to improve the yield of DRAM fabrication. However, finding a memory repair solution has been proved to be an NP-complete proble...
Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Che...
ISCAS
2008
IEEE
89views Hardware» more  ISCAS 2008»
16 years 27 days ago
Multi-loop efficient sturdy MASH delta-sigma modulators
— An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards h...
Nima Maghari, Un-Ku Moon
MTDT
1999
IEEE
88views Hardware» more  MTDT 1999»
15 years 10 months ago
Computing in Memory Architectures for Digital Image Processing
Continuing improvements in semiconductor fabrication density are enabling new classes of System-on-aChip architectures that combine extensive processing logic and high-density mem...
Luke Roth, Lee D. Coraor, David L. Landis, Paul T....
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
15 years 10 months ago
Fast Comparisons of Circuit Implementations
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
Shrirang K. Karandikar, Sachin S. Sapatnekar