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» Improving Java performance using hardware translation
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MSS
2000
IEEE
96views Hardware» more  MSS 2000»
15 years 11 months ago
APRIL: A Run-Time Library for Tape-Resident Data
Over the last decade, processors have made enormous gains in speed. But increase in the speed of the secondary and tertiary storage devices could not cope with these gains. The re...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 10 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
15 years 4 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 29 days ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
16 years 3 months ago
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Mi...