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ICDE
2005
IEEE
158views Database» more  ICDE 2005»
16 years 7 months ago
Cache-Conscious Automata for XML Filtering
Hardware cache behavior is an important factor in the performance of memory-resident, data-intensive systems such as XML filtering engines. A key data structure in several recent ...
Bingsheng He, Qiong Luo, Byron Choi
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
15 years 11 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
3DPVT
2004
IEEE
125views Visualization» more  3DPVT 2004»
15 years 10 months ago
GPU-Assisted Z-Field Simplification
Height fields and depth maps which we collectively refer to as z-fields, usually carry a lot of redundant information and are often used in real-time applications. This is the rea...
Alexander Bogomjakov, Craig Gotsman
PLDI
2009
ACM
16 years 1 months ago
Laminar: practical fine-grained decentralized information flow control
Decentralized information flow control (DIFC) is a promising model for writing programs with powerful, end-to-end security guarantees. Current DIFC systems that run on commodity ...
Indrajit Roy, Donald E. Porter, Michael D. Bond, K...
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
15 years 11 months ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...