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ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 10 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ICCV
2007
IEEE
16 years 8 months ago
Gradient Intensity-Based Registration of Multi-Modal Images of the Brain
We present a fast and accurate framework for registration of multi-modal volumetric images based on decoupled estimation of registration parameters utilizing spatial information i...
Parastoo Sadeghi, Ramtin Shams, Richard I. Hartley...
FPL
1997
Springer
125views Hardware» more  FPL 1997»
15 years 10 months ago
VPR: A new packing, placement and routing tool for FPGA research
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
Vaughn Betz, Jonathan Rose
ASPLOS
2010
ACM
16 years 28 days ago
COMPASS: a programmable data prefetcher using idle GPU shaders
A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores...
Dong Hyuk Woo, Hsien-Hsin S. Lee
ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
16 years 10 hour ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov