Sciweavers

2032 search results - page 142 / 407
» Improving Java performance using hardware translation
Sort
View
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
16 years 3 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
SIGMETRICS
2008
ACM
150views Hardware» more  SIGMETRICS 2008»
15 years 6 months ago
Performance of random medium access control, an asymptotic approach
Random Medium-Access-Control (MAC) algorithms have played an increasingly important role in the development of wired and wireless Local Area Networks (LANs) and yet the performanc...
Charles Bordenave, David McDonald, Alexandre Prout...
RTAS
2009
IEEE
16 years 1 months ago
The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
Stanley Bak, Deepti K. Chivukula, Olugbemiga Adeku...
IPPS
2003
IEEE
15 years 11 months ago
Flexible CoScheduling: Mitigating Load Imbalance and Improving Utilization of Heterogeneous Resources
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
Eitan Frachtenberg, Dror G. Feitelson, Fabrizio Pe...
SIPEW
2009
Springer
119views Hardware» more  SIPEW 2009»
16 years 28 days ago
A Tale of Two Processors: Revisiting the RISC-CISC Debate
The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions i...
Ciji Isen, Lizy K. John, Eugene John