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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
16 years 3 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
WEA
2010
Springer
289views Algorithms» more  WEA 2010»
16 years 1 months ago
Experiments with a Generic Dantzig-Wolfe Decomposition for Integer Programs
Abstract We report on experiments with turning the branch-price-andcut framework SCIP into a generic branch-price-and-cut solver. That is, given a mixed integer program (MIP), our ...
Gerald Gamrath, Marco E. Lübbecke
ACSAC
2009
IEEE
16 years 1 months ago
Analyzing Information Flow in JavaScript-Based Browser Extensions
JavaScript-based browser extensions (JSEs) enhance the core functionality of web browsers by improving their look and feel, and are widely available for commodity browsers. To ena...
Mohan Dhawan, Vinod Ganapathy
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
16 years 1 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...
HOST
2008
IEEE
16 years 28 days ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak po...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange...