20 search results - page 1 / 4 » Improvements to technology mapping for LUT-based FPGAs |
155
Voted
ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
147
Voted
FPGA
2000
ACM
15 years 9 months ago
2000
ACM
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
150
Voted
GLVLSI
1998
IEEE
15 years 10 months ago
1998
IEEE
A new technology mapper SELF-Map for LookUp Table LUT based Field Programmable Gate Arrays FPGAs is described. SELF-Map is based on the Stochastic Evolution SE algorithm. The stat...
176
Voted
ICCAD
2004
IEEE
16 years 2 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
149
Voted
GLVLSI
2009
IEEE
15 years 9 months ago
2009
IEEE
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...