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» Improvement of ASIC Design Processes
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DATE
2006
IEEE
108views Hardware» more  DATE 2006»
16 years 19 days ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
16 years 6 days ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
IUI
2004
ACM
16 years 17 hour ago
Evaluation of visual balance for automated layout
Layout refers to the process of determining the size and position of the visual objects in an information presentation. We introduce the WeightMap, a bitmap representation of the ...
Simon Lok, Steven Feiner, Gary Ngai
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 12 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
LAWEB
2003
IEEE
15 years 12 months ago
Cooperative Crawling
Web crawler design presents many different challenges: architecture, strategies, performance and more. One of the most important research topics concerns improving the selection o...
Marina Buzzi