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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 8 hour ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
INFOCOM
2000
IEEE
15 years 10 months ago
Comparisons of Packet Scheduling Algorithms for Fair Service Among Connections on the Internet
Abstract—We investigate the performance of TCP under three representatives of packet scheduling algorithms at the router. Our main focus is to investigate how fair service can be...
Go Hasegawa, Takahiro Matsuo, Masayuki Murata, Hid...
EUROMICRO
2003
IEEE
15 years 11 months ago
Extreme Programming: First Results from a Controlled Case Study
Extreme programming (XP) is the most well known agile software development method. Many experience reports have been published in recent years. Successful XP adoptions have howeve...
Pekka Abrahamsson
PPAM
2005
Springer
15 years 12 months ago
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
Éric Piel, Philippe Marquet, Julien Soula, ...
IEEEPACT
2006
IEEE
16 years 13 days ago
Prematerialization: reducing register pressure for free
Modern compiler transformations that eliminate redundant computations or reorder instructions, such as partial redundancy elimination and instruction scheduling, are very effectiv...
Ivan D. Baev, Richard E. Hank, David H. Gross