While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion and progressive integer linear programming (ILP). BoxRouter first uses a simple P...
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee