336 search results - page 61 / 68 » Improved data structures for fully dynamic biconnectivity |
136
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STACS
1992
Springer
15 years 10 months ago
1992
Springer
In this paper we give a practical and e cient output-sensitive algorithm for constructing the display of a polyhedral terrain. It runs in Od + nlog2 n time and uses On n space, wh...
152
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ICPP
2009
IEEE
16 years 14 days ago
2009
IEEE
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
170
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ISPW
1996
IEEE
15 years 10 months ago
1996
IEEE
A 1968 study of the software process led, inter alia, to the observation that the software process constitutes a feedback system. Attempts at its management and improvement must t...
179
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CODES
2005
IEEE
15 years 11 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
166
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...