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PCI
2005
Springer
15 years 12 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
DAC
1997
ACM
15 years 10 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
COMCOM
2002
86views more  COMCOM 2002»
15 years 6 months ago
The potential costs and benefits of long-term prefetching for content distribution
This paper examines the costs and potential benefits of long-term prefetching for content distribution. In traditional short-term prefetching, caches use recent access history to ...
Arun Venkataramani, Praveen Yalagandula, Ravi Kokk...
TKDE
1998
111views more  TKDE 1998»
15 years 6 months ago
Efficient Data Mining for Path Traversal Patterns
—In this paper, we explore a new data mining capability that involves mining path traversal patterns in a distributed information-providing environment where documents or objects...
Ming-Syan Chen, Jong Soo Park, Philip S. Yu
VTC
2010
IEEE
123views Communications» more  VTC 2010»
15 years 4 months ago
Downlink Power Control Scheme for Smart Antenna Based Wireless Systems
— In this paper, we propose a downlink power control scheme for a wireless system which utilizes a smart antenna technology for space division multiple access(SDMA). In the wirel...
Woongsup Lee, Dong-Ho Cho