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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
16 years 12 days ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
ICS
2005
Tsinghua U.
16 years 10 days ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
GECCO
2004
Springer
113views Optimization» more  GECCO 2004»
16 years 6 days ago
Implications of Epigenetic Learning Via Modification of Histones on Performance of Genetic Programming
Extending the notion of inheritable genotype in genetic programming (GP) from the common model of DNA into chromatin (DNA and histones), we propose an approach of embedding in GP a...
Ivan Tanev, Kikuo Yuta
ICSR
2004
Springer
16 years 6 days ago
Validating Quality of Service for Reusable Software Via Model-Integrated Distributed Continuous Quality Assurance
Quality assurance (QA) tasks, such as testing, profiling, and performance evaluation, have historically been done in-house on developer-generated workloads and regression suites. ...
Arvind S. Krishna, Douglas C. Schmidt, Atif M. Mem...
SCOPES
2004
Springer
16 years 5 days ago
Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition
Abstract. Synthesis of digital signal processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. I...
Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattac...